1. Field of the Invention
The present invention relates to a semiconductor manufacturing apparatus and a method of manufacturing a semiconductor device using the same. More particularly, the present invention relates to a scanner apparatus with a twin substrate stage, semiconductor photo equipment including the apparatus and a method of manufacturing a semiconductor device using the same.
2. Description of the Related Art
In the art of semiconductor manufacturing, an early semiconductor exposure apparatus was a proximity exposure apparatus. The proximity exposure apparatus gave way to a stepper apparatus, which, in turn, gave way to a scanner apparatus in the latter half of the 1990s. The scanner apparatus typically performs the exposure process by scanning light passing through a slit. The scanner apparatus has an advantage over the stepper apparatus in that a size of the projection lens may be reduced. The scanner apparatus may also average an error in the scanning direction arising from distortion or mislocation of the reticle. Accordingly, the scanner apparatus has been widely adopted for high-resolution exposure equipment.
FIG. 1 illustrates a block diagram of semiconductor photo equipment having a conventional scanner including a spinner apparatus 20 and a scanner apparatus 100. The spinner apparatus 20 and the scanner apparatus 100 are arranged to be inline. The spinner apparatus 20 performs photo resist deposition, baking and developing processes. The spinner apparatus 20 includes an edge exposure wafer (EEW) unit 25 that performs an edge exposure process for an edge of a wafer. A loading/unloading unit 10 for loading and unloading a cassette in which wafers are loaded is positioned on a side of the spinner apparatus 20. An interface unit 30 is disposed between the spinner apparatus 20 and the scanner apparatus 100.
FIG. 2 illustrates a sectional view of the scanner apparatus 100 of FIG. 1. Referring to FIG. 2, the scanner apparatus 100 includes twin substrate stages 120a and 120b installed on a base frame 110. Substrate stage 120a is a measuring stage and substrate stage 120b is an exposure stage. The measuring stage 120a includes a first chuck support 122a and a measuring chuck 124a. The exposure stage 120b includes a second chuck support 122b and an exposure chuck 124b. Metro frame 130 is installed above the respective substrate stages 120a and 120b. Light emission parts 142a and 142b and light absorption parts 144a and 144b that perform aligning and leveling processes are installed under the portion of the metro frame 130 disposed above the measuring stage 120a. A projection lens 160 and a reticle R and auto-focusing units 152a and 152b for performing the exposure process are respectively installed above and below the portion of the metro frame 130 disposed above the exposure stage 120b. Light for the exposure process is directed from a light source 170, e.g., a KrF or ArF excimer laser, which may be remote from the scanner apparatus. An arrow indicates a light path from the light source 170 to the projection lens 160.
A semiconductor photo process will now be described with reference to FIGS. 1 and 2. After a wafer W1 is loaded from the loading/unloading unit 10 to the spinner apparatus 20, a conventional photoresist coating process is performed. After the wafer W1 is transferred to the scanner apparatus 100 via the interface unit 30, the wafer W1 is loaded in a pre-alignment unit (not shown) to be aligned in a predetermined orientation. Next, the wafer W1 is conveyed to the alignment unit of the scanner apparatus 100 and loaded in the measuring stage 120a, after which the global aligning and leveling processes for the wafer W1 are performed.
After the above, the wafer W1 is conveyed to the exposure unit of the scanner apparatus 100 and loaded in the exposure substrate stage 120b. At the same time, a wafer W2 may be loaded in the measuring substrate stage 120a. In the exposure substrate stage 120b, an exposure process is performed by repeating step and scanning operations for the wafer W1. Concurrently, in the alignment unit, the global aligning and leveling processes may be performed for the wafer W2. Since the time for performing the global aligning and leveling processes in the alignment unit may be about 60% of the time for performing the exposure process in the exposure unit, the wafer W2, which has completed the global aligning and leveling processes, may need to wait to enter the next stage in order to perform the consecutive processes for multiple wafers.
When the exposure process for the wafer W1 is completed in the measuring stage 120a, the first W1 is transferred from the scanner apparatus 100 to the EEW unit 25 to go through an edge exposure process, after which the developing process for the wafer W1 may be performed by the spinner apparatus 20. When the developing process is completed, the wafer W1 is conveyed out of the semiconductor photo equipment by the loading/unloading unit 10.
In the process described above, the edge exposure is performed in the EEW unit 25 of the spinner apparatus 20, and thus the accuracy and precision of the process may be less than ideal, e.g., because a profile of the photo resist pattern may not be vertically formed. That is, since there is no precise exposure unit in the spinning apparatus, the accuracy and precision of the edge exposure process may be less than ideal. If the pattern is not too small, or if the size of the wafer is small, the precision and accuracy may not be a significant problem in the exposure process for the wafer edge. However, as the exposure pattern of the semiconductor wafer becomes increasingly small and the size of the wafer continues to grow, e.g., currently up to 12 inches, there is a need to enhance the accuracy and precision of the wafer edge exposure process. Furthermore, since the wafer edge exposure process is additionally performed in the EEW unit 25, the whole processing time of the semiconductor photo process is increased, thereby reducing productivity and yield.
The edge exposure process may have other deficiencies as well as those just described. A reticle having a shot area corresponding to 6 chips, 8 chips or 12 chips may be used in a main exposure process performed in the exposure unit. However, it may not be possible to use this same reticle for the edge exposure process. For example, in the conventional semiconductor manufacturing process illustrated FIG. 3A, a reticle R1 having a 6-chip shot area may be used to perform the exposure process for a center portion of the wafer as well as a portion contiguous to an edge of the wafer. The exposure result is illustrated in FIG. 3B, in which a shaded portion indicates a light reception region. As illustrated, the exposure process for the portion contiguous to the edge of the wafer, as well as the center portion of the wafer, is performed using the reticle R1 having the 6-chip shot area.
However, when forming deep features, e.g., in the case of a storage polysilicon process for forming a storage node of a One Cylinder Storage (OCS) structure, it may not be possible to perform the exposure process using the reticle R1 because the shot area may overlap the edge portion of the wafer. Where an OCS structure having a cylindrical pattern 15,000 Å or more in height is formed in the storage polysilicon process, severe particle generation may occur during the exposure process. In order to solve this problem, a reticle R2, illustrated in FIG. 4A, having a shot area that is less than the shot area of the reticle R1, may be used to perform the exposure process. FIG. 4B illustrates a plan view of a front surface of a wafer exposed through an exposure process using the reticle illustrated in FIG. 4A. Using this “page shot” exposure process, the shot area does not overlap the edge portion of the wafer and is located, instead, inside the border—even when the exposure process is performed for dies located on the wafer edge portion. However, the page shot process increases the number of shots required for exposing the whole surface of the wafer, thereby increasing the exposure processing time, reducing productivity and increasing processing costs.